1. Field of the Invention
The invention relates in general to a computer-aided design tool for helping an integrated circuit (IC) designer generate layouts for circuit devices implemented within an IC, and in particular to a method for producing layouts based on a scripted, hierarchical template specifying dimensions and relative positions of objects in a layout as functions of input parameters.
2. Description of Related Art
An IC designer typically uses computer-aided design tools to generate layouts for transistors, gates and many other types of electronic devices incorporated into an integrated circuit. For example FIG. 1 is a simplified sectional elevation view of an nMOS transistor 10 including a semiconductor substrate 11 having a p-doped well area 12 and n-doped source and drain areas 14 and 16, an insulating layer 18, a gate conductor 20, a source conductor 22, a drain conductor 24 and some polysilicon contacts 26. A layout for transistor 10 specifies the shapes and positions of the various areas or structures on each layer of the transistor. Computer-aided design (CAD) tools typically provide a graphic interface allowing the designer to draw each area or structure, and to treat it as a graphic object having an easily modifiable size, shape and position. For example FIG. 2 is a simplified plan view of a layout for transistor 10 of FIG. 1 that a designer might create using a conventional IC device layout CAD tool. FIG. 2 depicts the objects residing on the various layers of the transistor as superimposed, and although not shown in FIG. 2, the objects residing on each layer are usually depicted by separate colors.
IC fabricators impose various design rules on the layout of devices that can be implemented within an IC, placing limitations of the dimensions and spacing of objects residing on the various layers of an IC. For example for the transistors 10 of FIG. 2, design rules may place limitations on the width or length of the channel area between areas 14 and 16 and limitations on the amount by which well area 12 must overlap source and drain areas 14 and 16. The design rules vary with the type of semiconductor technology the fabricator employs.
Rather than directly designing every device included in an IC, a designer will, whenever possible, copy the layouts of standard devices (cells) included in a cell library, typically provided by the IC fabricator. When an IC fabricator develops a new IC technology, the fabricator establishes new design rules for that technology, and creates a new cell library providing cell layouts that are consistent with the new design rules. An IC designer developing a cell library will therefore have to design layouts for a large number cells, and that can be an expensive and time-consuming process. It is possible for the designer to save some time by creating the new cell library at least in part by modifying the layouts of cells of an existing cell library for some other IC technology so that the cells conform to new design rules. However, when a designer modifies a position or a dimension of any one object in a layout, he or she will often have to modify many other objects in the layout to avoid design rule violations or to otherwise maintain the proper spatial relationships between objects forming the device. Thus, for example, if a designer wants to decrease the width of gate 20 of transistor 10 of FIG. 2, the designer will have to also change the positions or dimensions of many of the other objects forming transistor 10 in a manner consistent with the new design rules.
Many cells included in a cell library will have somewhat similar topologies. For example, FIG. 3 shows an IC layout for a transistor 30 similar to transistor 10 of FIG. 3 but having a larger gate width. To create the layout for transistor 30, the designer could copy the layout for transistor 10, modify the dimensions of various objects included in the copy to accommodate the increased gate width and then add an extra set of contacts. FIG. 4 shows a “folded” transistor 40 that is similar to transistor 10 of FIG. 2 except that it has two gates 20 and two source areas 14, and it is possible for a designer to create the layout for transistor 40 by modifying the layout of transistor 10. However, while it may save some time to copy and then modify the layout of transistor 10 to produce the layouts of transistors 30 and 40, the designer may still require a substantial amount of time to determine whether and how to modify every object in the new transistor layouts.
What is needed is a method for a layout CAD tool enabling a designer to quickly and easily generate layouts for many topologically related devices without having to manually adjust numbers, positions or dimensions of objects in any of the generated layouts and having to carefully check each layout to ensure it satisfies design rules.